1. Field of the Invention
The present invention relates to a data selection circuit and, more particularly, to a driving circuit for a liquid crystal display (hereinafter referred to as LCD) of 1/n Duty-1/m Bias activating scheme.
2. Description of the Related Art
In the LCD, data, information etc. are displayed based on the combinations of activation and deactivation of the segments which are arranged separately on the LCD panel. As an LCD activating method, a 1/n Duty-1/m Bias activating scheme is well known. In this scheme, a segment signal (hereinafter referred to as a SEG signal) commonly supplied to n segments is used for driving n segments among all of the segments of the LCD, and the activation of each segment is controlled by switching the segment signal to m power source voltage levels, at preset timings based on 2.sup.n combinations of ON/OFF states which are supplied to the n segments. For instance, 1/2 Duty-1/2 Bias scheme, 1/3 Duty-1/3 Bias scheme, 1/4 Duty-1/4 Bias scheme, etc. are used.
FIG. 1 is a block diagram showing a general structure of an LCD driving circuit using a 1/3 Duty-1/3 Bias activating scheme. A timing signal generation circuit 105 generates timing signals D00 to D37. A data selection circuit 100 generates output signals G0 to G3 according to input n-bit select data, for example, 3-bit select data and a timing signal to turn ON/OFF analog switches 101 to 104. Each of the analog switches 101 to 104 is connected correspondingly to one of three types (m=3) of power sources, in which a power source voltage of V0 is used as a reference level. A COM signal creation circuit 106 generates COM signals which are inherent to respective segments as will be described later. For example, N data selection circuits 100 and N COM signal creation circuits 106 are provided according to the LCD panel.
FIG. 2 is a circuit diagram showing a construction of the conventional data selection circuit 100. Now, the conventional LCD driving circuit, particularly, a data selection circuit is explained. As shown in FIG. 2, the data selection circuit 100 includes a large number of NAND circuits and NOT circuits. A case wherein the LCD driving circuit drives three segments 121 to 123 in the seven-segment display device shown in FIG. 3 will be explained. The data selection circuit 100 of the LCD driving circuit is supplied with n-bit select data, for example, 3-bit select data S1, S2, S3 which indicate eight combinations (2.sup.3) of ON/OFF states of the three segments 121 to 123 (n=3) whose activation states are controlled by one SEG signal. Values of the respective bits S1 to S3 of the select data vary according to the ON or OFF states of the segments 121 to 123. Each value of the bits is set to "1" when the segment is set in the ON state, and set to "0" when the segment is set in the OFF state. The data selection circuit 100 is supplied with timing signals D00 to D07, D10 to D17, D20 to D27 and D30 to D37, as described later, from a timing signal generation circuit 105. The data selection circuit 100 outputs one of the timing signals D00 to D07 as a signal G0 according to the content of the 3-bit select data S1, S2, S3 supplied thereto. Likewise, the data selection circuit 100 selects signals from the respective groups of signals D10 to D17, D20 to D27, and D30 to D37 according to the select data, and outputs the selected signals as signals G1, G2 and GE. The output signals G1, G2 and GE are supplied to analog switches 101 to 104 shown in FIG. 1 as control signals to control the ON/OFF states of the analog switches. One ends of the current paths of the respective analog switches 101 to 104 are connected to power sources V0 to V3 having different supply voltage levels. A potential of one of the power sources V0 to V3 appears at the output terminal at preset timing by the ON/OFF control. As a result, the SEG signal is output according to select data, that is, the combination of values of the bit data items S1 to S3. The SEG signal is commonly supplied to the respective electrodes of the segments 121 to 123 of FIG. 3. On the other hand, the other electrodes of the segments 121 to 123 are respectively supplied with COM1 signal, COM2 signal and COM3 signal generated by the COM signal generation circuit 106 in FIG. 1. Therefore, as shown in FIG. 3, potential differences between the SEG signal and the respective COM signals, that is, SEG-COM1, SEG-COM2 and SEG-COM3 are supplied between the respective two electrodes of the segments 121 to 123 according to the select data. Depending upon the value of the potential differences between the SEG signal and the COM signals, selected one of the segments 121 to 123 are activated or deactivated so as to be set into the ON/OFF state according to select data.
However, the conventional data selection circuit has the following drawback. That is, in recent, multibit circuit configuration come to be frequently used in various circuits. If the conventional data selection circuit is formed in a multibit circuit configuration in order to cope with the above situation, the number of transistors constituting the data selection circuit is significantly increased with an increase in the number of select bits. For example, when n=m (n.gtoreq.2), as many as (n+1)(2.sup.n+3 +2.sup.n+2 -8) elements are required. When the number of select bits is increased, an area occupied by the data selection circuit in an LC or LSI circuit must be made extremely large. This cause a serious drawback in the design/manufacturing process.